1. Field of the Invention
The present invention relates to a charge pump circuit, and in particular to a charge pump circuit in a semiconductor integrated circuit (IC) for generating an elevated or lowered power level from an externally supplied power voltage.
2. Description of the Related Art
DRAMs (dynamic random access memories) and flash memories require elevated or lowered power levels due to their structures or the need to increase their operation speeds. It adds to the value of a chip as a product if elevated or lowered power levels can be generated by an internal power circuit incorporated in the chip.
A typical method for generating elevated or lowered power levels on a chip employs a charge pump circuit. A charge pump circuit on an IC usually incorporates transistors as rectification elements.
For example, a charge pump circuit disclosed in Japanese Laid-Open Publication No. 6-14529 has been proposed. Hereinafter, this conventional technique will be described with reference to the accompanying figures.
FIG. 18 is a circuit diagram illustrating the charge pump circuit described in the aforementioned literature. FIG. 19 is a diagram illustrating the operational waveforms of the charge pump circuit shown in FIG. 18. As shown in FIG. 18, the charge pump circuit includes rectification transistors Q1 and Q2, precharge transistors Q3 and Q4, and capacitors C1 and C2.
An input voltage Vdd is converted to an output voltage Vpp by the complementary action of the rectification transistor Q1 and the precharge transistor Q3 and the rectification transistor Q2 and the precharge transistor Q4 in response to a signal .phi.1 (having a first driving potential) and a signal .phi.2 (having a second driving potential).
Specifically, as the signal .phi.1 goes HIGH, the potential of a node N1 (coupled to a gate of the transistor Q1) is increased by the capacitor C1. The charge emerging at the node N1 is maintained at 2 Vdd while the signal .phi.1 is at the H (high) level (i.e., the Vdd level in this conventional example), and the potential of the gate of the transistor Q1 is sufficiently increased. Then, the charge at the node N1 is transferred to an output node Npp.
However, with respect to the precharge transistor Q3, for example, the charge emerging at a node N2 is output to the output node Npp and therefore decreases over time. Especially in the case where the input voltage Vdd is low, the gate potential of the precharge transistor Q3 is not sufficiently increased, so that the precharge transistor Q3 is incapable of sufficiently precharging the node N1 at Vdd. Thus, the potential of the node N1 cannot not be increased to 2Vdd responsive to the driving of the capacitor C1. As a result, the charge pump circuit outputs a charge (Vpp) which is smaller than the ideal charge, thereby resulting in a large loss in the voltage conversion process.
Even if the charge pump circuit operates in an ideal manner, the potential amplitudes of the transistors Q1 to Q4 will at best be equal to or lower than Vdd (because the gate potential is between Vdd and 2 Vdd). Therefore, under low voltage conditions where the input voltage Vdd is less than 1V, the on-off current difference of each of the transistors Q1 to Q4 becomes small. As a result, the charge stored in the capacitors C1 and C2 cannot be rapidly transferred to the output node Npp.
Furthermore, a timing control circuit TMG and driver circuits IV1 and IV2 for driving the charge pump circuit cannot rapidly drive a charge pump circuit (which constitutes a substantial load) under the low voltage conditions of the input voltage Vdd being less than 1 V. This results in the problem of an insufficient current being output from the charge pump circuit.